// IVB checksum: 3987518743
/*-----------------------------------------------------------------
File name     : vv_testbus_ad_config.e
Developers    : danilo
Created       : Fri Jul  8 11:54:04 2011
Description   :
Notes         :
-------------------------------------------------------------------
Copyright 2011 (c) 
-----------------------------------------------------------------*/
<'
package vv_testbus;

import vv_testbus/e/vv_testbus_ad_rsd_layering;

'>
<'
--------------------------------------------------------------------------------
-- Register definitions
--------------------------------------------------------------------------------

-- Add new register file kind
extend vr_ad_reg_file_kind : [EX_REG_FILE];


--       NAME         REGFILE      ADDR 
--       -------      -------      ---- 
reg_def  EX_CTRL_REG  EX_REG_FILE  0  {
    
--          NAME       TYPE            R/RW   RESET  COVER?
--          -----      ----            ----   -----  ------  
    reg_fld ctrl1    : uint(bits:16) :  RW  :   0   : cov;
    reg_fld ctrl2    : uint(bits:16) :  RW  :   0   : cov;
    
};

reg_def  EX_STATUS_REG  EX_REG_FILE  4 { 
    
--          NAME       TYPE            R/RW   RESET  COVER?
--          -----      ----            ----   -----  ------ 
    reg_fld status1  : uint(bits:16) :  RW  :   0   : cov;
    reg_fld status2  : uint(bits:16) :  RW  :   0   : cov;
    
};

'>
<'
--------------------------------------------------------------------------------
-- Extend the monitor to update the register model
--------------------------------------------------------------------------------
extend vv_testbus_bus_monitor {
      
    on transaction_end {
        
        if transaction.direction == WRITE {
            -- Write: updates the register reference model
            p_env.reg_addr_map.update(transaction.addr,pack(packing.low,transaction.get_data()),{});
        } else {
            -- Read: Compares against the reference model
            var b := p_env.reg_addr_map.compare_and_update(transaction.addr,pack(packing.low,transaction.get_data()));
        };
    };
    
};
'>
<'
--------------------------------------------------------------------------------
-- Instantiation of:
-- o Address map
-- o Register file
-- o Register sequence driver (RSD)
-- 
-- Note: We recommend to instantiate the register-file under the module UVC unit
-- The address-map and the RSD should be instantiate under the top level env.
-- We used vv_testbus_env just for simplicity.
--------------------------------------------------------------------------------
extend vv_ahblite_env {
   
    -- Register file instantiation
    reg_file : EX_REG_FILE vr_ad_reg_file;
        keep soft reg_file.size == 0x100;
    
    -- Address map instantiation
    reg_addr_map : vr_ad_map;
    
    -- Register sequence driver (RSD) instantiation
    rsd : vr_ad_sequence_driver is instance;
        -- Connect the rsd to the address map
        keep rsd.addr_map == read_only(reg_addr_map);
        -- Specify one of the UVC master drivers as the default 
        -- BFM sequence driver
    keep rsd.default_bfm_sd == read_only(master.as_a(ACTIVE vv_testbus_master).driver);
    
    -- Map the register-file in the address-map
    post_generate() is also {
        reg_addr_map.add_with_offset(0,reg_file);
    };
     
  
  
};


'>
